CMOS Strain Engineering

Beyond 90 nm technology node, the strain engineering is the key technology to boost the channel mobility and enhance the performance of CMOS transistors. Strained engineering process, typically enhancing the CMOS device performance by 10~20 %, benefits from the advantage of low cost, compatibility with CMOS process and high controllability. In addition to the mobility enhancement, strain engineering also helps reduce leakage and improves retention time in non-volatile memory devices.


In the study of CMOS strain engineering, we had great research experiences and strong collaborations with the world-leading electronics companies in Taiwan. Current research projects include 1) strained material growth (ex. Ge/GeSi-on-Si heterostructure), 2) simulation in devices (ex. TSV stress and strain simulation by Ansys) and 3) strain measurement (Raman spectroscopy).

 

 

Related Publications:

  1. C.-Y. Peng, Y.-C. Fu, C.-F. Huang, Y.-J. Yang, S.-T. Chang, and C.W. Liu, “Effects of Applied Mechanical Uniaxial and Biaxial Tensile Strain on the Flatband Voltage of (001), (110), and (111) Metal-Oxide-Silicon Capacitors,” IEEE Trans. on Electron Devices, Vol. 56, No. 8, pp. 1736-1745, 2009.
  2. C.-Y. Peng, C.-F. Huang, Y.-C. Fu, Y.-H. Yang, C.-Y. Lai, S.-T. Chang, and C. W. Liu, “Comprehensive study of the Raman shifts of strained silicon and germanium,” J. Appl. Phys., Vol. 105, 083537, 2009.
  3. Y.-J. Yang, W. S. Ho, C.-F. Huang, S. T. Chang, and C. W. Liu, “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect-transistors,” Appl. Phys. Lett., Vol. 91, 102103, 2007; also in Virtual Journal of Nanoscale Science & Technology, Vol. 16, Issue. 12, 2007.